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DATA SHEET
4GB Fully Buffered DIMM
EBE42FE8ACFR
Specifications
* Density: 4GB * Organization 512M words x 72 bits, 4 ranks * Mounting 36 pieces of 1G bits DDR2 SDRAM sealed in FBGA * Package 240-pin fully buffered, socket type dual in line memory module (FB-DIMM) PCB height: 30.35mm Lead pitch: 1.00mm Advanced Memory Buffer (AMB): 655-ball FCBGA Lead-free (RoHS compliant) * Power supply DDR2 SDRAM: VDD = 1.8V 0.1V AMB: VCC = 1.5V +0.075V/ -0.045V * Data rate: 667Mbps (max.) * Eight internal banks for concurrent operation (components) * Interface: SSTL_18 * Burst lengths (BL): 4, 8 * /CAS Latency (CL): 3, 4, 5 * Precharge: auto precharge option for each burst access * Refresh: auto-refresh, self-refresh * Refresh cycles: 8192 cycles/64ms Average refresh period 7.8s at 0C TC +85C 3.9s at +85C < TC +95C * Operating case temperature range TC = 0C to +95C
Features
* JEDEC standard Raw Card AE Design * Industry Standard Advanced Memory Buffer (AMB) * High-speed differential point-to-point link interface at 1.5V (JEDEC spec) 14 north-bound (NB) high speed serial lanes 10 south-bound (SB) high speed serial lanes * Various features/modes: MemBIST and IBIST test functions Transparent mode and direct access mode for DRAM testing Interface for a thermal sensor and status indicator * Channel error detection and reporting * Automatic DDR2 SDRAM bus and channel calibration * SPD (serial presence detect) with 1piece of 256 byte serial EEPROM Note: Warranty void if removed DIMM heat spreader.
Performance
FB-DIMM System clock frequency 167MHz Speed grade PC2-5300F Peak channel throughput 8.0GByte/s FB-DIMM link data rate 4.0Gbps DDR2 SDRAM Speed Grade DDR2-667 (5-5-5) DDR data rate 667Mbps
Document No. E1328E30 (Ver. 3.0) Date Published October 2008 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2008
EBE42FE8ACFR
Ordering Information
Part number EBE42FE8ACFR-6E-E DIMM speed grade PC2-5300F Component JEDEC speed bin (CL-tRCD-tRP) DDR2-667 (5-5-5) Mounted devices*
1
Mounted AMB* IDT Rev. L4
2
EDE1108ACSE-8E-E EDE1108ACSE-6E-E
Notes: 1. Please refer to the EDE1104ACSE, EDE1108ACSE, EDE1116ACSE datasheet (E0975E) for detailed operation part and timing waveforms. 2. Please refer to the following documents for detailed operation part and timing waveforms. Advanced Memory Buffer (AMB) specification FB-DIMM Architecture and Protocol specification
Part Number
E B E 42 F E 8 A C F R - 6E - E
Elpida Memory
Type B: Module
Environment code E: Lead Free (RoHS compliant)
Product Family E: DDR2
DRAM Speed Grade 6E: DDR2-667 (5-5-5)
AMB Device Information R: IDT, Rev.L4 Module Outline F: 240-pin DIMM
Density / Rank 42: 4GB/4-rank Module Type F: Fully Buffered Mono Density E: 1Gbit
Mono Organization 8: x8
Die Rev. (Mono)
Power Supply, Interface A: 1.8V, SSTL_1.8
Data Sheet E1328E30 (Ver. 3.0)
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Advanced Memory Buffer Overview
The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification. It supports DDR2 SDRAM main memory. The AMB allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. The AMB interface is responsible for handling FB-DIMM channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the FB-DIMM channel. The FB-DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface. FB-DIMMs use commodity DRAMs isolated from the channel behind a buffer on the DIMM. The memory capacity is 288 devices per channel and total memory capacity scales with DRAM bit density. The AMB is the buffer that isolates the DRAMs from the channel.
Advanced Memory Buffer Functionality The AMB will perform the following FB-DIMM channel functions. * Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and Protocol Specification to align the clocks and the frame boundaries, verify channel connectivity, and identify AMB DIMM position. * Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific AMB or DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames. * If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames. * Detects errors on the channel and reports them to the host memory controller. * Support the FB-DIMM configuration register set as defined in the register chapters. * Acts as DRAM memory buffer for all read, write, and configuration accesses addressed to the DIMM. * Provides a read buffer FIFO and a write buffer FIFO. * Supports an SMBus protocol interface for access to the AMB configuration registers. * Provides logic to support MemBIST and IBIST design for test functions. * Provides a register interface for the thermal sensor and status indicator. * Functions as a repeater to extend the maximum length of FB-DIMM links.
Data Sheet E1328E30 (Ver. 3.0)
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EBE42FE8ACFR
Advanced Memory Buffer Block Diagram
Southbound 10x2 Data in 10x2 Southbound Data out
Reference clock
1x2
PLL
Data merge
RE-time Re-synch
Demux
PISO
/RESET
Reset control
10x12 10x12
Thermal sensor
Link init SM and control and CSRs
failover
IBIST-RX
Init patterns
Mux
4 DRAM clock
4 DRAM clock
IBIST-TX
Command decoder & CRC check
LAI logic DRAM Command Command out DRAM interface Data out
Mux
DDR state controller and CSRs
Core controller and CSRs
Write data FIFO
External MemBIST DDR calibration
Mux
DRAM address and command copy1 24 DRAM address and command copy2 A2 for the ECC DRAMs A6 for the ECC DRAMs 4 DRAM chip select
72+18x2
24
Data in
DRAM data and strobes
Data CRC generator and Read FIFO LAI controller
Sync & idle pattern generator
IBIST-TX
IBIST-RX
NB LAI Buffer
Mux
Link init SM and control and CSRs
SMBus
SMBus controller
failover 14x6x2
PISO
14x12
Demux
Re-synch RE-time
Data merge
Northbound 14x2 Data Out
14x2 Northbound Data In
Note: This figure is a conceptual block diagram of the AMB's data flow and clock domains.
Data Sheet E1328E30 (Ver. 3.0)
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Interfaces Figure Block Diagram AMB Interfaces shows the AMB and all of its interfaces. They consist of two FB-DIMM links, one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on an FB-DIMM.
Memory Interface
NB FBD out Link SB FBD in Link AMB
NB FBD in Link SB FBD out Link SMB
Block Diagram AMB Interfaces
Interface Topology The FB-DIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8 DIMMs per channel. The host sends data on the southbound link to the first DIMM where it is received and redriven to the second DIMM. On the southbound data path each DIMM receives the data and again re-drives the data to the next DIMM until the last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the direction on the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives the data to the next DIMM until the host is reached.
Host Southbound Nourthbound
AMB
AMB
AMB
AMB
n/c
Block Diagram FB-DIMM Channel Southbound and Northbound Paths
Data Sheet E1328E30 (Ver. 3.0)
5
Secondary or to optional next FBD
Primary or Host Direction
n/c
EBE42FE8ACFR
High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces The AMB supports one FB-DIMM channel consisting of two bidirectional link interfaces using high-speed differential point-to-point electrical signaling. The southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent DIMM in the host direction. The southbound output link forwards this same data to the next FB-DIMM. The northbound input link is 14 lanes wide and carries read return data or status information from the next FB-DIMM in the chain back towards the host. The northbound output link forwards this information back towards the host and multiplexes in any read return data or status information that is generated internally. Data and commands sent to the DRAMs travel southbound on 10 primary differential signal line pairs. Data received from the DRAMs and status information travel northbound on 14 primary differential pairs. Data and commands sent to the adjacent DIMM upstream are repeated and travel further southbound on 10 secondary differential pairs. Data and status information received from the adjacent DIMM upstream travel further northbound on 14 secondary differential pairs.
DDR2 Channel The DDR2 channel on the AMB supports direct connection to DDR2 SDRAMs. The DDR2 channel supports four ranks of eight banks with 15 row/column request, 64 data, and eight check-bit signals. There are two copies of address and command signals excluding chip select, to support DIMM routing and electrical requirements. Four transfer bursts are driven on the data and check-bit lines at 667MHz. Propagation delays between read data/checkbit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware state machines using write/read trial and error. Hardware aligns the read data and check-bits to a single core clock. The AMB provides four copies of the command clock phase references (CLK [3:0]) and write data/check-bit strobes (DQSs) for each DRAM nibble.
SMBus Slave interface The AMB supports an SMBus interface to allow system access to configuration register independent of the FB-DIMM link. The AMB will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100kHz. SMBus access to the AMB may be a requirement to boot and to set link strength, frequency and other parameters needed to insure robust configurations. It is also required for diagnostic support when the link is down. The SMBus address straps located on the DIMM connector are used by the unique ID.
Data Sheet E1328E30 (Ver. 3.0)
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EBE42FE8ACFR
Block Diagram
CS3 CS2 CS1 /CS0 DQS0 /DQS0 DQS9 8 DM /CS DQS /DQS /RDQS DQ0 D0 to DQ7 8 DM /CS /RDQS DQ0 to DQ7 DQS /DQS
DQ0 to DQ7
D9
8
DM /CS DQS /DQS /RDQS DQ0 D18 to DQ7
8
DM /CS DQS /DQS /RDQS DQ0 D27 to DQ7
DQS1 /DQS1 DQS10 DQ8 to DQ15 8
DM /CS /RDQS DQ0 to DQ7
DQS /DQS
D1
8
DM /CS /RDQS DQ0 to DQ7
DQS /DQS
D10
8
DM /CS DQS /DQS /RDQS DQ0 D19 to DQ7
8
DM /CS DQS /DQS /RDQS DQ0 D28 to DQ7
DQS2 /DQS2 DQS11 8 DM /CS /RDQS DQ0 to DQ7 DQS /DQS
DQ16 to DQ23
D2
8
DM /CS /RDQS DQ0 to DQ7
DQS /DQS
D11
8
DM /CS DQS /DQS /RDQS DQ0 D20 to DQ7
8
DM /CS DQS /DQS /RDQS DQ0 D29 to DQ7
DQS3 /DQS3 DQS12 8 DM /CS /RDQS DQ0 to DQ7 DQS /DQS
DQ24 to DQ31
D3
8
DM /CS /RDQS DQ0 to DQ7
DQS /DQS
D12
8
DM /CS DQS /DQS /RDQS DQ0 D21 to DQ7
8
DM CS DQS /DQS /RDQS DQ0 D30 to DQ7
DQS4 /DQS4 DQS13 8 DM /CS /RDQS DQ0 to DQ7 DQS /DQS
DQ32 to DQ39
D4
8
DM /CS /RDQS DQ0 to DQ7
DQS /DQS
D13
8
DM /CS DQS /DQS /RDQS DQ0 D22 to DQ7
8
DM /CS DQS /DQS /RDQS DQ0 D31 to DQ7
DQS5 /DQS5 DQS14 8 DQ40 to DQ47 DM /CS /RDQS DQ0 to DQ7 DQS /DQS 8 DM /CS /RDQS DQ0 to DQ7 DQS /DQS 8 DM /CS DQS /DQS /RDQS DQ0 D23 to DQ7 8 DM /CS DQS /DQS /RDQS DQ0 D32 to DQ7
D5
D14
DQS6 /DQS6 DQS15 8 DM /CS /RDQS DQ0 to DQ7 DQS /DQS 8 DM /CS /RDQS DQ0 to DQ7 DQS /DQS 8 DM /CS DQS /DQS /RDQS DQ0 to DQ7 D24 8 DM /CS DQS /DQS /RDQS DQ0 to DQ7 D33
DQ48 to DQ55
D6
D15
DQS7 /DQS7 DQS16 DQ56 to DQ63 8 DM /CS /RDQS DQ0 to DQ7 DQS /DQS 8 DM /CS /RDQS DQ0 to DQ7 DQS /DQS 8 DM /CS DQS /DQS /RDQS DQ0 D25 to DQ7 8 DM /CS DQS /DQS /RDQS DQ0 D34 to DQ7
D7
D16
DQS8 /DQS8 DQS17 8 DM /CS /RDQS DQ0 to DQ7 DQS /DQS 8 DM /CS /RDQS DQ0 to DQ7 DQS /DQS 8 DM /CS DQS /DQS /RDQS DQ0 D26 to DQ7 8 DM /CS DQS /DQS /RDQS DQ0 D35 to DQ7
CB0 to CB7
D8
D17
PN0 to PN13 /PN0 to /PN13 PS0 to PS9 /PS0 to /PS9 DQ0 to DQ63 CB0 to CB7 DQS0 to DQS17 /DQS0 to /DQS8 SCL SDA SA1 to SA2 SA0 /RESET SCK/ /SCK
SN0 to SN13 /SN0 to /SN13 SS0 to SS9 /SS0 to /SS9
Serial PD
SCL SCL
U0
SDA
SDA
VTT VCC
Terminators AMB SPD, AMB
A M B
VDDSPD WP A0 A1 A2 /CS0 -> /CS (D0 to D8) /CS1 -> /CS (D9 to D17) D0 to D35, AMB VDD /CS2 -> /CS (D18 to D26) SA0 SA1 SA2 /CS3 -> /CS (D27 to D35) D0 to D35 VREF CKE0 -> CKE (D0 to D8, D18 to D26) CKE1 -> CKE (D9 to D17, D27 to D35) D0 to D35, SPD, AMB * D0 to D35 : 1G bits DDR2 SDRAM VSS ODT0A -> ODT (D9 to D17) U0 : 256 bytes EEPROM ODT0B -> ODT (D0 to D8) ODT1 -> ODT (D18 to D26) ODT2 -> ODT (D27 to D35) Notes: BA0 to BA2 (all SDRAMs) 1. DQ wiring may be changed within a byte. A0, A1, A3 to A5, A7 to A13 -> (all SDRAMs) 2. There are two physical copies of each address/command excluding ECCA2/ECCA6. A2, A6 -> A2, A6 (D0 to D7, D9 to D16, D18 to D25, D27 to D34) 3. There are four physical copies of each clock. ECCA2,ECCA6 -> A2, A6 (D8, D17, D26, D35) /RAS (all SDRAMs) /CAS (all SDRAMs) /WE (all SDRAMs) CK/ /CK (all SDRAMs)
All address/command/control/clock
VTT
Data Sheet E1328E30 (Ver. 3.0)
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EBE42FE8ACFR
Pin Configurations
Front side 1 pin 68 pin 69 pin 120 pin
121 pin Back side
188 pin 189 pin
240 pin
Front side No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Name VDD VDD VDD VSS VDD VDD VDD VSS VCC VCC VSS VCC VCC VSS VTT VID1 No. Name 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 VSS PN5 /PN5 VSS PN13 /PN13 VSS VSS NC NC VSS VSS PN12 /PN12 VSS PN6 /PN6 VSS PN7 /PN7 VSS PN8 /PN8 VSS PN9 /PN9 VSS PN10 /PN10 VSS PN11 /PN11 VSS VSS PS0 No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Name /PS0 VSS PS1 /PS1 VSS PS2 /PS2 VSS PS3 /PS3 VSS PS4 /PS4 VSS VSS NC NC VSS VSS PS9 /PS9 VSS PS5 /PS5 VSS PS6 /PS6 VSS PS7 /PS7 VSS PS8 /PS8 VSS NC No. 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name NC VSS VDD VDD VSS VDD VDD VDD VSS VDD VDD VTT SA2 SDA SCL
Back side No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Name VDD VDD VDD VSS VDD VDD VDD VSS VCC VCC VSS VCC VCC VSS VTT VID0 No. 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 Name VSS SN5 /SN5 VSS SN13 /SN13 VSS VSS NC NC VSS VSS SN12 /SN12 VSS SN6 /SN6 VSS SN7 /SN7 VSS SN8 /SN8 VSS SN9 /SN9 VSS SN10 /SN10 VSS SN11 /SN11 VSS VSS SS0 No. 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 Name No. /SS0 VSS SS1 /SS1 VSS SS2 /SS2 VSS SS3 /SS3 VSS SS4 /SS4 VSS VSS NC NC VSS VSS SS9 /SS9 VSS SS5 /SS5 VSS SS6 /SS6 VSS SS7 /SS7 VSS SS8 /SS8 VSS NC 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Name NC VSS SCK /SCK VSS VDD VDD VDD VSS VDD VDD VTT VDDSPD SA0 SA1
/RESET 52 VSS NC NC VSS PN0 /PN0 VSS PN1 /PN1 VSS PN2 /PN2 VSS PN3 /PN3 VSS PN4 /PN4 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
M_TEST 172 VSS NC NC VSS SN0 /SN0 VSS SN1 /SN1 VSS SN2 /SN2 VSS SN3 /SN3 VSS SN4 /SN4 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190
Data Sheet E1328E30 (Ver. 3.0)
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EBE42FE8ACFR
Pin Description
Pin name SCK, /SCK PN0 to PN13, /PN0 to /PN13 PS0 to PS9, /PS0 to /PS9 SN0 to SN13, /SN0 to /SN13 SS0 to SS9, /SS0 to /SS9 SCL SDA SA0 to SA2*
1 2
Pin Type Input Output Input Input Output Input Input / Output Input Input Input
3
Function System clock input Primary northbound data Primary southbound data Secondary northbound data Secondary southbound data Serial presence detect (SPD) clock input SPD data and AMB SMBus address/data SPD address inputs Voltage ID AMB reset signal VREF margin test input No connection AMB core power and AMB channel interface power (1.5V) DRAM power and AMB DRAM I/O power (1.8V) DRAM address, Command and clock termination voltage (VDD/2) SPD power (3.3V) Ground
VID0 to VID1* /RESET M_TEST* NC VCC VDD VTT VDDSPD VSS
Input Power supply Power supply Power supply Power supply
Notes: 1. They are also used to select the DIMM number in the AMB. 2. These pins must be unconnected. 3. Don't connect in a system.
Data Sheet E1328E30 (Ver. 3.0)
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EBE42FE8ACFR
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS AMB core power voltage relative to VSS DRAM interface power voltage relative to VSS Termination voltage relative to VSS Storage temperature Symbol VIN/VOUT VCC VDD VTT Tstg Value -0.3 to +1.75 -0.3 to +1.75 -0.5 to +2.30 -0.5 to +2.30 -55 to +100 Unit V V V V C Note
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Operating Temperature Conditions
Parameter SDRAM component case temperature AMB component case temperature Symbol TC_DRAM TC_AMB Value 0 to +95 110 Unit C C Note 1
Note: 1. Supporting 0C to +85C and being able to extend to +95C with doubling auto-refresh commands in frequency to a 32ms period (tREFI = 3.9s) and higher temperature self-refresh entry via the control of EMRS (2) bit A7 is required. DC Operating Conditions
Parameter AMB supply voltage DDR2 SDRAM supply voltage Input termination voltage EEPROM supply voltage SPD input high voltage SPD input low voltage RESET input high voltage RESET input low voltage Leakage current (RESET) Leakage current (link) Symbol VCC VDD VTT VDDSPD VIH (DC) VIL (DC) VIH (DC) VIL (DC) IL IL min. 1.455 1.7 0.48 x VDD 3.0 2.1 -- 1.0 -- -90 -5 typ. 1.50 1.8 0.50 x VDD 3.3 -- -- -- -- -- -- max. 1.575 1.9 0.52 x VDD 3.6 VDDSPD 0.8 -- 0.5 90 5 Unit V V V V V V V V A A 1 1 2 2 2 3 Note
Notes: 1. Applies for SMB and SPD bus signals. 2. Applies for AMB CMOS signal /RESET. 3. For all other AMB related DC parameters, please refer to the high-speed differential link interface specification.
Data Sheet E1328E30 (Ver. 3.0)
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EBE42FE8ACFR
AMB Component Timing For purposes of IDD testing, the following parameters are to be utilized.
Parameter EI Assertion pass-thru timing EI deassertion pass-thru timing EI assertion duration Resample pass-thru time Resynch pass-thru time Bit lock Interval Frame lock Interval tBitLock tFrameLock Symbol tEI propagate tEID tEI min. -- -- 100 -- -- -- -- typ. -- -- -- 1.075 2.075 -- -- max. 4 bit lock -- -- -- 119 154 Units clks clks clks ns ns frames frames Note
Note: 1. The EI stands for Electrical Idle. Power Specification Parameter and Test Conditions
-6E Frequency (Mbps) Parameter Idle Current, single or last DIMM Symbol 667 Power Supply max. @1.5V Idd_Idle_0 @1.8V Total @1.5V Idle Current, first DIMM Idd_Idle_1 @1.8V Total @1.5V Active Power Idd_Active_1 @1.8V Total @1.5V Active Power, Idd_Active_2 data pass through @1.8V Total @1.5V Idd_Training (for AMB spec. @1.8V Not in SPD) Total 1.60 2.12 5.88 2.30 2.11 6.98 2.90 3.08 9.76 2.40 2.10 7.12 2.30 2.03 6.83 Unit A A W A A W A A W A A W A A W Conditions L0 state, idle (0 BW) Primary channel enabled, Secondary channel disabled CKE high. Command and address lines stable. DRAM clock active. L0 state, idle (0 BW) Primary and secondary channels enabled CKE high. Command and address lines stable. DRAM clock active. L0 state 50% DRAM BW, 67% read, 33% write. Primary and secondary channels enabled. DRAM clock active, CKE high. L0 state 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and secondary channels enabled. CKE high. Command and address lines stable. DRAM clock active. Primary and secondary channels enabled. 100% toggle on all channel lanes DRAMs idle. 0 BW. CKE high, Command and address lines stable. DRAM clock active. Note
Training
Data Sheet E1328E30 (Ver. 3.0)
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EBE42FE8ACFR
Reference Clock Input Specifications*1
Parameter Reference clock frequency@ 4.0 Gb/s (nominal 166.67MHz) Single-ended maximum voltage Single-ended minimum voltage Differential voltage high Differential voltage low Absolute crossing point VCross variation AC common mode Rising and falling edge rates % Mismatch between rise and fall edge rates Duty cycle of reference clock Ringback voltage threshold Allowed time before ringback Clock leakage current Clock input capacitance Clock input capacitance delta Transport delay Symbol fRefclk-4.0 Vmax Vmin VRefclk-diff-ih VRefclk-diff-il VCross VCross-delta VSCK-cm-acp-p ERRefclk-diff-Rise, ERRefclk-diff-Fall ERRefclk-Match TRefclk-Dutycycle VRB-diff TStable II_CK CI_CK CI_CK () TD NSAMPLE Reference clock jitter (rms), filtered min. 158.33 -0.3 150 250 0.6 40 -100 500 -10 0.5 -0.25 10
12
max. 166.75 1.15 -150 550 140 225 4.0 20 60 100 10 2.0 0.25 5 3.0 30 0.75
Units MHz V V mV mV mV mV mV V/ns % % mV ps A pF pF ns periods ps ps ps
Notes 2, 3, 4 5, 7 5, 8 6 6 5, 9, 10 5, 9, 11 12 6, 13 6, 14 6 6, 15 6, 15 16, 17 17 Difference between RefClk and RefClk# input capacitance 18, 19 20 21, 22
TREF-JITTER-RMS
Reference clock jitter (peak-to-peak) due TREF-SSCp-p to spectrum clocking effects Reference clock jitter difference between TREF-JITTERadjacent AMB DELTA
23
Notes: 1. For details, refer to the JEDEC specification "FB-DIMM High Speed Differential PTP Link at 1.5V". 2. The nominal reference clock frequency is determined by the data frequency of the link divided by 2 times the fixed PLL multiplication factor for the FB-DIMM channel (6:1). fdata = 2000MHz for a 4.0Gbps FBDIMM channel and so on. 3. Measured with SSC disabled. Enabling SSC will reduce the reference clock frequency. 4. Not all FB-DIMM agents will support all frequencies; compliance to the frequency specifications is only required for those data rates that are supported by the device under test. 5. Measurement taken from single-ended waveform. 6. Measurement taken from differential waveform. 7. Defined as the maximum instantaneous voltage including overshoot. 8. Defined as the minimum instantaneous voltage including undershoot. 9. Measured at the crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. 10. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 11. Defined as the total variation of all crossing voltages of rising REFCLK+ and falling REFCLK-. This is the maximum allowed variance in for any particular system. 12. The majority of the reference clock AC common mode occurs at high frequency (i.e., the reference clock frequency).
Data Sheet E1328E30 (Ver. 3.0)
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EBE42FE8ACFR
13. Measured from -150mV to + 150mV on the differential waveform. The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential 0V crossing. 14. Edge rate matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a 75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median crosspoint is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. The rising edge rate of REFCLK+ should be compared to the falling edge rate of REFCLK-. The maximum allowed difference should not exceed 20% of the slowest edge 15. Tstable is the time the differential clock must maintain a minimum 150mV differential voltage after rising /falling edges before it is allowed to droop back into the 100mV differential range. 16.Measured with a single-ended input voltage of 1V. 17. Applies to RefClk and RefClk#. 18. This parameter is not a direct clock output parameter but it indirectly determines the clock output parameter TREF-JITTER. 19. The net transport delay is the difference in time of flight between associated data and clock paths. The data path is defined from the reference clock source, through the TX, to data arrival at the data sampling point in the RX. The clock path is defined from the reference clock source to clock arrival at the same sampling point. The path delays are caused by copper trace routes, on-chip routing, on-chip buffering, etc. They include the time-of-flight of interpolators or other clock adjustment mechanisms. They do not include the phase delays caused by finite PLL loop bandwidth because these delays are modeled by the PLL transfer functions. 20. Direct measurement of phase jitter records over NSAMPLE periods may be impractical. It is expected that the jitter will be measured over a smaller, yet statistically significant, sample size and the total jitter at NSAMPLE samples extrapolated from an estimate of the sigma of the random jitter components. 21. Measured with SSC enabled on reference clock generator. 22. As "measured" after the phase jitter filter. This number is separate from the receiver jitter budget that is defined by the TRX-Total-MIN parameters. 23. This maximum value is below the noise floor of some test equipment.
Data Sheet E1328E30 (Ver. 3.0)
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EBE42FE8ACFR
Differential Transmitter Output Specifications*1
Parameter Differential peak-to-peak output voltage for large voltage swing Differential peak-to-peak output voltage for regular voltage swing Differential peak-to-peak output voltage for small voltage swing DC common code output voltage for large voltage swing DC common code output voltage for small voltage swing De-emphasized differential output voltage ratio for -3.5dB de-emphasis De-emphasized differential output voltage ratio for -6dB de-emphasis Symbol VTX-DIFFp-p_L min. 900 max. 1300 Unit mV Comments VTX-DIFFp-p = 2 x | VTX-D+ - VTX-D- | Measured as note 2 VTX-DIFFp-p = 2 x | VTX-D+ - VTX-D- | Measured as note 2 VTX-DIFFp-p = 2 x | VTX-D+ - VTX-D- | Measured as note 2 Defined as: VTX-CM = DC (avg) of |VTX-D+ + VTX-D-|/2 Measured as note 2 Defined as: VTX-CM = DC (avg) of |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 3 2, 4, 5
VTX-DIFFp-p_R
800
mV
VTX-DIFFp-p_S
520
mV
VTX-CM_L
375
mV
VTX-CM_S
135
280
mV
VTX-DE-3.5-Ratio
-3.0 -5.0
-4.0 -7.0
dB
VTX-DE-6.0-Ratio
dB
2, 4, 5 VTX-CM-AC = Max |VTX-D+ + VTX-D-|/2 - Min |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 6 VTX-CM-AC = Max |VTX-D+ + VTX-D-|/2 - Min |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 6 VTX-CM-AC = Max |VTX-D+ + VTX-D-|/2 - Min |VTX-D+ + VTX-D-|/2 Measured as note 2. See also note 6 7, 8
AC peak-to-peak common mode output voltage for large VTX-CM-ACp-p L swing AC peak-to-peak common mode output voltage for regular swing
90
mV
VTX-CM-ACp-p R
80
mV
AC peak-to-peak common mode output voltage for small VTX-CM-ACp-p S swing Maximum single-ended voltage in EI condition, DC + AC Maximum single-ended voltage in EI condition, DC only Maximum peak-to-peak differential voltage in EI condition Single-ended voltage (w.r.t.VSS) on D+/DMinimum TX eye width Maximum TX deterministic jitter Instantaneous pulse width
70
mV
VTX-IDLE-SE
50
mV
VTX-IDLE-SE-DC
20
mV
7, 8, 9
VTX-IDLE-DIFFp-p VTX-SE TTX-Eye-MIN TTX-DJ-DD TTX-PULSE
-75 0.7 0.85 30 8 6
40 750 0.2 90 20
mV mV UI UI UI ps ps dB dB
8 2, 10 2, 11, 12 2, 11, 12, 13 14 Given by 20%-80% voltage levels. Measured as note 2
Differential TX output rise/fall TTX-RISE, time TTX-FALL Mismatch between rise and TTX-RF-MISMATCH fall times Differential return loss Common mode return loss RLTX-DIFF RLTX-CM
Measured over 0.1GHz to 2.4GHz. See also note 15 Measured over 0.1GHz to 2.4GHz. See also note 15
Data Sheet E1328E30 (Ver. 3.0)
14
EBE42FE8ACFR
Parameter Transmitter termination resistance Symbol RTX min. 41 max. 55 Unit Comments 16 RTX-Match-DC = 2x|RTX-D+ - RTX-D-| / (RTX-D+ + RTX-D-) Bounds are applied separately to high and low output voltage states 17, 19 18, 19 20 20 21
D+/D- TX resistance difference
RTX-Match-DC
4
%
Lane-to-lane skew at TX Lane-to-lane skew at TX Maximum TX Drift (resync mode) Maximum TX Drift (resample mode only) Bit Error Ratio
LTX-SKEW 1 LTX-SKEW 2

100 + 3UI ps 100 + 2UI ps 240 120 10
-12
TTX-DRIFT-RESYNC TTX-DRIFTRESAMPLE BER
ps ps
Notes: 1. For details, refer to the JEDEC specification "FB-DIMM High Speed Differential PTP Link at 1.5V". 2. Specified at the package pins into a timing and voltage compliance test load. Common-mode measurements to be performed using a 101010 pattern. 3. The transmitter designer should not artificially elevate the common mode in order to meet this specification. 4. This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. 5. De-emphasis shall be disabled in the calibration state. 6. Includes all sources of AC common mode noise. 7. Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as the Electrical Idle condition. 8. Specified at the package pins into a voltage compliance test load. Transmitters must meet both singleended and differential output EI specifications. 9. This specification, considered with VRX-IDLE-SE-DC, implies a maximum 15mV single-ended DC offset between TX and RX pins during the electrical idle condition. This in turn allows a ground offset between adjacent FB-DIMM agents of 26mV when worst case termination resistance matching is considered. 10. The maximum value is specified to be at least (VTX-DIFFp-p L / 4) + VTX-CM L + (VTX-CM-ACp-p / 2) 11. This number does not include the effects of SSC or reference clock jitter. 12. These timing specifications apply to resync mode only. 13. Defined as the dual-dirac deterministic jitter. 14. Pulse width measured at 0 V differential. 15. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully designed. 16. The termination small signal resistance; tolerance across voltages from 100mV to 400mV shall not exceed 5. with regard to the average of the values measured at 100mV and at 400mV for that pin. 17. Lane to Lane skew at the Transmitter pins for an end component. 18. Lane to Lane skew at the Transmitter pins for an intermediate component (assuming zero Lane to Lane skew at the Receiver pins of the incoming PORT). 19. This is a static skew. An FB-DIMM component is not allowed to change its lane to lane phase relationship after initialization. 20. Measured from the reference clock edge to the center of the output eye. This specification must be met across specified voltage and temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of the receiver. 21. BER per differential lane.
Data Sheet E1328E30 (Ver. 3.0)
15
EBE42FE8ACFR
Differential Receiver Input Specifications*1
Parameter Differential peak-to-peak input voltage Maximum single-ended voltage for EI condition (AC + DC) Maximum single-ended voltage for EI condition (DC only) Maximum peak-to-peak differential voltage for EI condition Single-ended voltage (w.r.t. VSS) on D+/DSingle-pulse peak differential input voltage Amplitude ratio between adjacent symbols, 1100mV < VRX-DIFFp-p <= 1300mV Amplitude ratio between adjacent symbols, VRX-DIFFp-p <= 1100mV Maximum RX inherent deterministic timing error Single-pulse width at zero-voltage crossing Single-pulse width at minimumlevel crossing Differential RX input rise/fall time Symbol VRX-DIFFp-p VRX-IDLE-SE VRX-IDLE-SE-DC VRX-IDLE-DIFFp-p VRX-SE VRX-DIFF-PULSE VRX-DIFF-ADJ RATIO- HI VRX-DIFF-ADJ RATIO min. 170 -300 85 max. 1300 65 35 65 900 3.0 Unit mV mV mV mV mV mV Comments VRX-DIFFp-p = 2x|VRX-D+ -VRX-D-| Measured as note 2 3, 4, 5, 6 3, 4, 5, 6, 7 4, 5, 6 5 5, 8 5, 9
0.55 0.2 50
4.0 0.4 0.3 UI UI UI UI ps
5, 9 5, 10, 11 5, 10, 11, 12 5, 8 5, 8 Given by 20%-80% voltage levels. Defined as: VRX-CM = DC (avg) of |VRX-D+ + VRX-D-|/2 Measured as note 2. See also note 13 VRX-CM-AC = Max |VRX-D+ + VRX-D-|/2 - Min |VRX-D+ + VRX-D-|/2 Measured as note 2 14 Measured over 0.1GHz to 2.4GHz. See also note 15 Measured over 0.1GHz to 2.4GHz. See also note 15 16 RRX-Match-DC = 2x|RRX-D+ - RRX-D-| / (RRX-D+ + RRX-D-) Lane-to-lane PCB skew at the receiver that must be tolerated. See also note 17 18 19 20
Maximum RX inherent timing error TRX-TJ-MAX TRX-DJ-DD TRX-PW-ZC TRX-PW-ML TRX-RISE, TRX-FALL
Common mode of the input voltage VRX-CM
120
400
mV
AC peak-to-peak common mode of VRX-CM-ACp-p input voltage Ratio of VRX-CM-ACp-p to minimum VRX-DIFFp-p Differential return loss Common mode return loss RX termination resistance D+/D- RX resistance difference VRX-CM-EH-Ratio RLRX-DIFF RLRX-CM RRX RRX-Match-DC
270
mV
9 6 41
45 55 4
% dB dB %
Lane-to-lane PCB skew at Rx Minimum RX Drift Tolerance Minimum data tracking 3dB bandwidth Electrical idle entry detect time Electrical idle exit detect time Bit Error Ratio
LRX-PCB-SKEW TRX-DRIFT FTRK TEI-ENTRY DETECT TEI-EXIT -DETECT BER
400 0.2
6 60 30 10
-12
UI ps MHz ns ns
21
Data Sheet E1328E30 (Ver. 3.0)
16
EBE42FE8ACFR
Notes: 1. For details, refer to the JEDEC specification "FB-DIMM High Speed Differential PTP Link at 1.5V". 2. Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the pad will be lower than at the pin. 3. Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as the Electrical Idle condition. Worst-case margins are determined by comparing EI levels with common mode levels during normal operation for the case with transmitter using small voltage swing. 4. Multiple lanes need to detect the EI condition before the device can act upon the EI detection. 5. Specified at the package pins into a timing and voltage compliance test setup. 6. Receiver designers may implement either single-ended or differential EI detection. Receivers must meet the specification that corresponds to the implemented detection circuit. 7. This specification, considered with VTX-IDLE-SE-DC, implies a maximum 15mV single-ended DC offset between TX and RX pins during the electrical idle condition. This in turn allows a ground offset between adjacent FB-DIMM agents of 26mV when worst case termination resistance matching is considered. 8. The single-pulse mask provides sufficient symbol energy for reliable RX reception. Each symbol must comply with both the single-pulse mask and the cumulative eye mask. 9. The relative amplitude ratio limit between adjacent symbols prevents excessive inter-symbol interference in the Rx. Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols. 10. This number does not include the effects of SSC or reference clock jitter. 11. This number includes setup and hold of the RX sampling flop. 12. Defined as the dual-dirac deterministic timing error. 13. Allows for 15mV DC offset between transmit and receive devices. 14. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peak-topeak common mode specification. For example, if VRX-DIFFp-p is 200mV, the maximum AC peak-topeak common mode is the lesser of (200mV x 0.45 = 90mV) and VRX-CM-ACp-p. 15. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully designed. 16. The termination small signal resistance; tolerance across voltages from 100mV to 400mV shall not exceed 5. with regard to the average of the values measured at 100mV and at 400mV for that pin. 17. This number represents the lane-to-lane skew between TX and RX pins and does not include the transmitter output skew from the component driving the signal to the receiver. This is one component of the end-to-end channel skew in the AMB specification. 18. Measured from the reference clock edge to the center of the input eye. This specification must be met across specified voltage and temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of the receiver. 19. This bandwidth number assumes the specified minimum data transition density. Maximum jitter at 0.2MHz is 0.05UI. 20. The specified time includes the time required to forward the EI entry condition. 21. BER per differential lane.
Data Sheet E1328E30 (Ver. 3.0)
17
EBE42FE8ACFR
Serial PD Matrix for FB-DIMM
Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Function described Number of serial PD bytes written / SPD device size / CRC coverage SPD revision Key byte / DRAM device type Voltage levels of this assembly SDRAM addressing Module physical attributes Module Type / Thickness Module organization Fine timebase (FTB) dividend / divisor Medium timebase dividend Medium timebase divisor SDRAM minimum cycle time (tCK (min.)) SDRAM maximum cycle time (tCK (max.)) SDRAM /CAS latencies supported SDRAM minimum /CAS latencies time (tCAS) SDRAM write recovery times supported SDRAM write recovery time (tWR) SDRAM write latencies supported SDRAM additive latencies supported SDRAM minimum /RAS to /CAS delay (tRCD) SDRAM minimum row active to row active delay (tRRD) SDRAM minimum row precharge time (tRP) SDRAM upper nibbles for tRAS and tRC SDRAM minimum active to precharge time (tRAS) SDRAM minimum auto-refresh to active /auto-refresh time (tRC) SDRAM minimum refresh recovery time delay (tRFC), LSB SDRAM minimum refresh recovery time delay (tRFC), MSB SDRAM Internal write to read command delay (tWTR) SDRAM Internal read to precharge command delay (tRTP) SDRAM burst lengths supported SDRAM terminations supported SDRAM drivers supported SDRAM average refresh interval (tREFI) / double refresh mode bit / high temperature self-refresh rate support indication Tcasemax (TC (max.)) delta / DT4R4W delta Psi T-A SDRAM at still air SDRAM DT0 SDRAM DT2Q SDRAM DT2P SDRAM DT3N SDRAM DT4R / mode bit SDRAM DT5B SDRAM DT7 45ns 60ns 127.5ns 127.5ns 7.5ns 7.5ns BL = 4, 8 ODT = 50, 75, 150 Supported 7.8s Double/HT refresh 95C/ 0.26C * * * * * * * *
3 3 3 3 3 3 3 3
Byte value 116 Revision 1.1 DDR2 SDRAM FB-DIMM VDD = 1.8V, VCC = 1.5V
Hex value 92H 11H 09H 12H
14-row, 10-column, 8-bank 45H 8.2mm FB-DIMM 4 ranks / 8bits 24H 07H 21H 00H 1 4 3.00ns 8ns CL = 3, 4, 5 15ns WR = 2 to 5 15ns WL = 2 to 8 AL = 0 to 4 15ns 7.5ns 15ns 01H 04H 0CH 20H 33H 3CH 42H 3CH 72H 50H 3CH 1EH 3CH 00H B4H F0H FEH 01H 1EH 1EH 03H 07H 01H C2H 51H xx xx xx xx xx xx xx xx
Data Sheet E1328E30 (Ver. 3.0)
18
EBE42FE8ACFR
Byte No. 42 to 74 75 76 77 78 79 80 81 to 93 94 to 97 98 99 100 Function described Reserved AMB QR control setting FBD ODT CTRL ranks 0 and 1, RD and WRT FBD ODT CTRL ranks 2 and 3, RD FBD ODT definition for ranks 2 and 3 FBD ODT definition for ranks 0 and 1 Reserved AMB personality bytes Reserved AMB case temperature maximum (Tcase (max.)) Category byte Reserved Planar/FDHS 150/150 150/150 QR = Enable, ECCA2/ECCA6 and ODT1/2 functionality Byte value Hex value 00H 35H 44H 6FH AAH AAH 00H xx 00H xx 0AH 00H xx Elpida Memory Elpida Memory 02H FEH xx Year code (BCD) Date code (BCD) xx xx xx xx EBE42FE8ACFR Initial (Space) Elpida Memory Elpida Memory xx 30H 20H 02H FEH xx xx 00H 00H
101 to 116 AMB personality bytes 117 118 119 120 121 Module ID: manufacturer's JEDEC ID code Module ID: manufacturer's JEDEC ID code Module ID: manufacturing location Module ID: manufacturing date Module ID: manufacturing date
122 to 125 Module ID: module serial number 126 to 127 Cyclical redundancy code 128 to 145 Module part number 146 147 148 149 150 151 Module revision code Module revision code SDRAM manufacturer's JEDEC ID code SDRAM manufacturer's JEDEC ID code Informal AMB content revision tag (MSB) Informal AMB content revision tag (LSB)
152 to 175 Manufacturer's specific data 176 to 255 Open for customer use
Remark IDD: DRAM current, ICC: AMB current Notes: 1. Based on DDR2 SDRAM component specification. 2. Refer to JESD51-3 "Low effective thermal conductivity Test board for leaded surface mount packages" under JESD51-2 standard. 3. DT parameter is derived as following: DTx = IDDx x VDD x Psi T-A, where IDDx definition is based on JEDEC DDR2 SDRAM component specification and at VDD=1.9V, it is the datasheet (worst case) value, and Psi T-A is the programmed value of Psi T-A (value in SPD Byte 33).
Data Sheet E1328E30 (Ver. 3.0)
19
EBE42FE8ACFR
Physical Outline
Unit: mm
Front side
74.675
(DATUM -A-)
Full DIMM heat spreader
8.20 max. 5.20 max. 3.00 max.
D27
3.90
D10 D19
D29 D2
D12 D21
D0
1
D4
D23
D6
D25
120
4.00 min.
AMB
D31
D14
D33
D16
1.25 5.175
R0.75 67.00 133.35
B 51.00
A
1.27 0.10
Back side
120
9.50 17.30 30.35
5.00 1.50 0.10
121
240
D18
3.00
D1
D20
D3 D30
D26 D17
D8 D35
D22 D13
D5 D32
D24 D15
D7 D34
2.50
D9
D28 D11
FULL R
Detail A
2.50 0.20
Detail B 1.00
0.20 0.15
(DATUM -A-) 2.50 FULL R
0.80 0.05 Tie bar keep out zone
3.80
0.40 min.
ECA-TS2-0269-01
Data Sheet E1328E30 (Ver. 3.0)
20
EBE42FE8ACFR
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E1328E30 (Ver. 3.0)
21
EBE42FE8ACFR
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0706
Data Sheet E1328E30 (Ver. 3.0)
22

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